This invention relates to read and write memory accesses in multi-bank memory devices. In particular, this invention relates to reducing the number of clock cycles incurred when accessing multi-bank memory devices.
Computers and other electronic systems usually include memory subsystems. Typical memory subsystems include a memory controller that controls communications between the CPU and various memory devices. Memory devices, such as, for example, DRAMs (dynamic random access memories), are widely used in computer circuits because of their large storage capacity and relatively low power requirements. A DRAM can contain several internal banks of memory cells, which are organized into rows and columns. Typically, a non-banked memory device is one in which the memory device has one memory array with one set of row-column decoding circuitry and one set of data sensing circuitry, while a multi-banked memory device has at least two separate memory arrays, each operated independently with separate row-column decoding circuitry and data sensing circuitry. One advantage of multi-banked memory devices is increased parallelization of internal operations, which increases memory device throughput.
Any memory cell in a particular row of a particular bank of a multi-banked memory device can be accessed after that bank and row are “activated”. Activated banks or rows stay activated for a given period of time, after which they are de-activated and then re-activated for further accesses.
During read accesses to a DRAM, there is at least a one clock cycle delay from the time a valid read address is provided to the DRAM to the moment data corresponding to that read address appears at the outputs of the DRAM (assuming that the bank and row accessed by that read address have already been activated). However, the relative timing of addresses and data for write accesses to a DRAM is different from that of addresses and data for read accesses. During write accesses to a DRAM, a write address is typically provided to the DRAM at substantially the same time as data to be written to that write address. When a write access follows a read access and vice-versa, at least a one clock cycle delay results from this difference in read and write accesses. This one clock cycle delay multiplied by the vast number of read and write accesses typically performed by computers and other systems with such memory can significantly reduce the overall speed/bandwidth performance of those computers and systems.
In view of the foregoing, it would be desirable to reduce read-write access delay and write-read access delay in multi-bank memory devices.